Binary storage element



J 1963 o. E. BLOCK 3,076,182

, BINARY s'romcs mam Filed Jan. 11, 1960 2 Shoots-Shut 1 i myiszvron I 90mm BLOCK ATTORNEY AGENT CLOOK Jan. 29, 1963 o. BLOCK 3,076,132

BINARY sromcs mam? Filed Jan. 11, 1960 2 Shasta-Shoot 2 INVENT OR.

DONALD E. 'LOCK BY wk ATTO N Y' 5 'AsNT United States Patent 3,076,182 BINARY STORAGE ELEMENT Donald E. Block, Pacific Palisades, Calih, assignor to the United States of America as represented by the Secretary of the Air Force Filed Jan. 11, 1960, Ser. No. 1,831 Claims. (Cl. 340-174) The purpose of this invention is to provide a bistable binary storage element capable of (1) providing a continuous DC. output voltage at either of two levels corresponding to the two binary digits and (2) being deener gized without destroying the stored information. The permanent storage feature is achieved by utilizing the non-destructive read-out properties of a transfiuxor, as will be described in more detail with reference to the accompanying drawing in which FIG. 1 is a schematic diagram of a binary storage element in accordance with the invention incorporated in a two-stage shift register, and

FIG. 2 is a modification of the storage element shown in FIG. 1.

Referring to the drawing, the bistable storage element utilizes a three-apertured transfluxor 1 which, as known in the art, is a closed magnetic core having a central aperture 2, a setting aperture 3 and an output aperature 4. The core is driven with a constant frequency, constant amplitude alternating current applied over conductor 5 linked through the output aperture 4. An output winding 6 also links this aperture and has an output voltage induced in it as a result of the driving current. The transfluxor 1 is always in one of two magnetic states termed the set condition and the blocked condition. When in the set condition, the driving current in line 5 produces a relatively large output voltage in winding 6. In the blocked condition, the driving current does not produce any appreciable voltage in winding 6. For cores now in use, the ratio of these outputs is greater than 6 to 1.

The transfiuxor 1 is placed in the set condition by causing a current to flow in setting windIng 7 linked through central aperture 2 and setting aperture3. The transfluxor is placed in the blocked condition by causing a current to flow in blocking winding 8 linked through the central aperture 2. These currents are controlled by an input gate 9 in accordance with the binary input in electrical form which is applied to input line 10.

In the embodiment shown in the drawing the input signals are of a relatively high level representing the binary digit 1 or of a relatively low level representing the binary digit 0. These levels may be 0 volts and -6 volts relative to ground, respectively, as illustrated in the drawing.

These signals are applied to the base of NPN transistor 11 and, after inversion by PNP transistor 12, to the base of NPN transistor 13. Negative clock pulses, the periodic synchronizing pulses commonly used in computer systems, are applied between the emitter electrodes of transistors 11 and 13 and ground. The operation of the gating circuit 9 is as follows:

Assumer the potential of input l'ne 10 to be zero volts representing the binary digit 1. This causes the base of NPN transistor 11 to be at zero or ground potential and the base of NPN transistor 13 to be at 6 volts relative to ground. The negative potential of the transistor 13 base is due to the signal inversion produced by PNP transistor 12. With the base of this transistor at ground po-' tential there is no emitter current and therefore substantially no collector current flowing through resistor 15. With no drop across this resistor the collector of transistor 12 and the base of transistor 13 are at 6 volts potential relative to ground. Under the above conditions, the application of a negative clock pulse to the emitters of tran- 3,076,182 Patented Jan. 29, 1963 sistors 11 and 13 produces an emitter current in transistor 11 but not in transistor 13 because of the negative bias on the base of the, latter transistor. The pulse of emitter current in'transistor 11 results in a pulse of collector current in setting winding 7 which places the transfluxor in the set condition.

When the potential on input line 10 is -6 volts representing the binary digit 0, the base of transistor 11 is held at -6 volts relative to ground, but the base of transistor 12 is at zero or ground potential. The latter condition is due to PNP inverting transistor "12 in which the negative baseresults in an emitter current and, as a result, a collector current through resistor 15 raising the voltage of the collector and the base of transistor 13 to ground potential. Therefore, the negative clock pulse produces a pulse of collector current in transistor 13 which flows in blocking winding 8 placing the transfluxor in the blocked condition. No collector current flows in transistor 11 in this instance because of the 6 volt bias on its base.

As stated earlier a relatively large A.C. voltage is induced in output winding 6 when the transfiuxor is in the set condition and little or no voltage is induced when in the blocked condition. The larger A.C. output therefore indicates that the transfluxor is storing a binary 1 and the smaller A.C. output indicates that the transfiuxor is storing a binary 0. These A.C. indications may be changed to DC. indications of the type applied to input line 10 by means of a peak detector 16. The peak detector comprises a PNP junction transistor 17 having the A.C. output voltage in winding 6 applied between its base and a point of positive bias potential V The bias voltage V is made greater than the maximum peak A.C. output voltage when the transfluxor core is blocked and less than the minimum peak A.C. output voltage when the core is set. Therefore, for all output voltages less than V the emitter-base junction of the transistor is biased in the back direction and there is no emitter current, but for all A.C. output voltages having peak values exceeding V the emitter-base junction is biased in the forward direction during the peak of the negative half-cycle causing a pulse of emitter current to flow.

In a practical circuit V may have a value of about 1.5 volts. The collector-base iunction is biased in the backward direction, i.e. the collector negative relative to the base, by means of a voltage divider 18-19 connected between ground and a point of negative potential V The magnitude of V and the sizes of resistors 1819 are so chosen that, in the absence of a collector current, output conductor 20 has a potential of substantially -6 volts representing a binary 0. This is the condition that exists when the A.C. output peak voltage is less than V indicating that a binary 0 is stored by the transfiuxor. When the peak value of the A.C. output voltage exceeds V pulses of emitter current and corresponding pulses of collector current flow during each negative half-cycle. These pulses of collector. current charge condenser 21 with the polarity shown and thereby raise the potential of conductor 20 to near zero or ground potential indicating that a binary l is stored by the transfluxor.

FIG. 2 shows a modification of input gate 9 in which the inverting transistor 12 of FIG. 1 is eliminated, but which requires a second clock pulse with a different reference level. Referring to this figure, the modified gate 9' comprises a transistor 11 operated by clock A pulses in the same manner as transistor 11 of FIG. 1 and a PNP transistor 21,- which replaces NPN transistor 13 of FIG. 1. Transistor 21 is operated by clock B gating pulses, which are positive-going and have a reference of 6 volts corresponding to the binary 0 voltage on input line 10. When line 10 is at ground potential, representing a binary 1 input, transistor 21 is not conductive since the clock B pulse raises the emitter only to ground potential. However.

when line is at --6 volts, representing a binary 0 input, the clock B pulse raises the emitter above base potential producing an emitter current and a corresponding collector current which flows in blocking winding 8. Winding 8 links the core in this case in the opposite direction from that in FIG. 1 because of the opposite direction of the collector current flowiin the PNP transistor.

Power failure and subsequent reenergization do not affect the set or blocked condition that the transfiuxor was in at the time the power failure occu'red and therefore do not affect the stored information. Binary storage ele ments of the above described type may be used as logical building blocks in many computer applications. For example, these elements may be cascaded to form a shift register in the manner shown in FIG. 1 where a two-stage shift register is illustrated.

I claim:

1. A binary storage device comprising a transfiuxor having a central aperture, a setting aperture and an output aperture; an alternating current energizing circuit linked through said output aperture; an alternating current out put circuit linked through said output aperture, a biased peak detector coupled to said output circuit and having a predetermined direct output voltage when the peak alternating voltage in said output circuit is less than the peak detector bias and an increased direct output voltage when the peak alternating voltage in said output circuit exceeds the peak detector bias; and a gate circuit having an input circuit, a first gates output circuit linked through said setting and central apertures and a second gate output circuit linked through said central aperture, said gate circuit operating when said input circuit is energized by a voltage representative of a binary l to energize said first gate output circuit and operating when said input circuit is energized by a voltage representative of a binary 0 to energize said second gate output circuit.

2. Apparatus as claimed in claim 1 in which said gate circuit comprises first and second NPN junction transistors, means for connecting said input circuit to the base of said first transistor, a signal inverting device connected between said input circuit and the base of said second transistor, means connecting the collectors of said first and second transistors to said first and second gate output circuits, respectively, and means for applying periodic negative-going clock pulses simultaneously to the emitters of said transistors.

3. Apparatus as claimed in claim 2 in which said signal inverting device is a PNP junction transistor having its base connected to said input circuit, its collector connected to the base of said second transistor and its emitter connected to a point of reference potential.

4. Apparatus as claimed in claim 1 in which said gate circuit comprises an NPN junction transistor and a PNP junction transistor, means for connecting said input circuit directly to the bases of said transistors, means connecting the collector of said NPN transistor to said first gate output circuit, means connecting the collector of said PNP transistor to said second gate output circuit, means for applying periodic negative-going clock pulses to the emitter of said NPN transistor, and means for applying positive-going clock pulses superimposed on a fixed negative bias potential to the emitter of said PNP transistor.

5. Apparatus as claimed in claim 1 in which said peak detector comprises a PNP junction transistor, means connecting said alternating current output circuit between the base of said transistor and a point of positive bias potential, a parallel resistance-capacitance time constant circuit connected between the collector of said transistor and a point of negative potential, said collector serving as the output terminal of said detector, and means connecting the emitter of said transistor to a point of reference potential.

References Cited in the file of this patent UNITED STATES PATENTS 

1. A BINARY STORAGE DEVICE COMPRISING A TRANSFLUXOR HAVING A CENTRAL APERTURE, A SETTING APERTURE AND AN OUTPUT APERTURE; AN ALTERNATING CURRENT ENERGIZING CIRCUIT LINKED THROUGH SAID OUTPUT APERTURE; AN ALTERNATING CURRENT OUTPUT CIRCUIT LINKED THROUGH SAID OUTPUT APERTURE, A BIASED PEAK DETECTOR COUPLED TO SAID OUTPUT CIRCUIT AND HAVING A PREDETERMINED DIRECT OUTPUT VOLTAGE WHEN THE PEAK ALTERNATING VOLTAGE IN SAID OUTPUT CIRCUIT IS LESS THAN THE PEAK DETECTOR BIAS AND AN INCREASED DIRECT OUTPUT VOLTAGE WHEN THE PEAK ALTERNATING VOLTAGE IN SAID OUTPUT CIRCUIT EXCEEDS THE PEAK DETECTOR BIAS; AND A GATE CIRCUIT HAVING 